The object of a phase locking circuit is to lock onto the phase of an incoming signal. Digital phase locks generally comprise a phase comparator which generates a difference voltage proportional to a phase error, i.e, the phase difference between the phase of the phase lock circuit and that of the incoming signal. The difference voltage is filtered by a loop filter to eliminate noise. Signals are received from the output of the loop filter for controlling a clock so that the phase of the clock signal is advanced or retarded. In standard step correctors, the clock phase is corrected in standard steps upward or downward. A phase lock operating on this advance/retard principle is called lead/lag phase lock.
Digital phase locks operating on lead/lag principle use digital filters of a type known as sequential filters, as their loop filters.
FIG. 1 shows schematically the structure of a digital phase lock operating on the lead/lag principle. The phase lock comprises a phase comparator 10, a loop filter 11, a clock 12, a local oscillator 14 and a divider 13. Lead or lag pulses are generated in the phase comparator 10 according to whether the phase of The local oscillator is ahead or behind compared with an incoming signal to the comparator 10. Errors caused by noise can be eliminated from a phase correction signal by means of the loop filter 11. An output signal of the filter controls a clock signal of the phase-locked loop in such a way that its phase is advanced or retarded by removing or adding samples, respectively.
FIG. 2a illustrates the structure of a conventional loop filter of a lead/lag phase lock. The filter comprises three counters 20, 21, 22 and two OR gates 23, 24. Lead and lag pulses are counted in the filter by separate N counters 20 and 21. In addition to this, both pulses are brought via the OR gate 23 to a common M counter 22. If one of the N counters 20, 21 fills up before the common M counter 22, a lead pulse 25 or a lag pulse 26, respectively, is sent from the filter, depending on which one of the counters filled up. After the pulse has been sent, all counters are set to zero by means of a signal 27. On the other hand, if the common M counter 22 fills up at first, all counters are set to zero by the signal 27 and no correction is made. The lengths of the counters are selected in such a way that N&lt;M&lt;2N. The bandwidth and correction rate of the filter can thus be influenced by the values of the numbers N and M. An advantage of this filter is good attenuation in loop operation, but a drawback is slow correction.
Another conventional manner of filtering a phase correction signal is presented in FIG. 2b. The filter in question is a conventional digital infinite impulse Response (IIR) filter comprising two amplifiers 30, 31, a summer 32 and a delay element 33, followed by a threshold detector 34. The integration time of the filter is selected by the amplification parameters a, b of amplifiers 30 and 31 in the filter. The threshold detector K operates as follows:
if input signal of detector .gtoreq. threshold, output is +1 PA1 if absolute value of input signal of detector &lt; threshold, output is 0 PA1 if input signal of detector .gtoreq. threshold, output is -1.
Accordingly, both lead and lag pulses are filtered by the same filter, and there are no separate counters. The correction rate of the filter according to FIG. 2b is relatively good, but is a problem slowly attenuating oscillation in the correction process of the loop is a problem.
The capacity of a spread spectrum receiver is substantially influenced by the phase accuracy of the spreading code. An error of 0.5 chips, for instance, causes a power loss of 6 dB. Phase tracking accuracy and especially variance therein are affected, except for a code tracking algorithm, by the quality of the loop filter. It has been noticed that, in practice the code tracking algorithm operating on the lead/lag principle functions well in receivers. However, the loop filters used therein have drawbacks, and an aim of this invention is to improve such loop filters.
When conventional loop filters are used, the variance in phase error increases rapidly and instantaneous error caused by noise therefore is big. When a phase step response exceeding a given threshold is also involved, correction of a phase error may be uncontrolled, with the loop being thrown into a continuous correction state. This situation can be corrected by lengthening the integration time of the filter. However, the integration time cannot be lengthened endlessly. Due to the Doppler effect, the receiver is then no longer capable of tracking the variance in a received signal.
FIG. 3a shows an output signal (I) of an integrator of a traditional loop filter as a function of time in a situation when a clock periods deviates by two samples from the correct value. In FIG. 3b, respectively, a signal is at the output of a threshold detector of the loop filter. In the conventional loop filter, exceeding the threshold affects the output signal of the integrator, so that the phase is corrected by one sample too much. Then the loop receives a control signal of opposite sign and the integrator integrates in the opposite direction until the threshold is exceeded. When a negative threshold is exceeded, a negative clock control pulse is generated. Such a to-and-fro oscillation may last for a long time, even in the presence of noise.